PXD20RM Datasheet, PDF (1397/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

wait state for every access; refer to Chapter 19, Error Correction Status Module (ECSM), for more
information. Table 40-1 lists the various combinations of read and write operations to SRAM and the
number of wait states used for each operation. The table columns contain the following information:
Current operation Lists the type of SRAM operation executing currently
Previous operation
Lists the valid types of SRAM operations that can precede the current SRAM
operation (valid operation during the preceding clock)
Wait states
Lists the number of wait states (bus clocks) the operation requires which depends
on the combination of the current and previous operation
Table 40-1. Number of wait states required for SRAM operations
Current operation
Previous operation
Number of wait states required¹
Idle
Pipelined read
1
Burst read
Read
64-bit write
8-, 16-, or 32-bit write
2
0
(read from the same address)
1
(read from a different address)
Pipelined read
Read
0
Idle
Pipelined read
1,0,0,0
Burst read
Burst read
64-bit write
8-, 16-, or 32-bit write
2,0,0,0
0,0,0,0
(read from the same address)
1,0,0,0
(read from a different address)
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
40-3