PXD20RM Datasheet, PDF (589/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Field
PRE
Table 13-8. DRAMC_TC0 field descriptions (continued)
Description
Time-out. Any active bank, that has no outstanding requests, is automatically precharged by the
DRAMC after this time-out has elapsed since the last access to the bank. This time can be set short,
which results in open banks being precharged quite fast to long, which results in open banks left
open for a long time. The value is a time count in DRAM clock periods.
13.3.2.2.2 DRAMC Time Configuration Register 1 (DRAMC_TC1)
Address: Base + 0x0008
0
1
2
3
4
5
6
7
8
9
10
11
R
RFC
W
WR1
Reset 0
0
0
0
0
0
0
0
0
0
0
0
Access: User read/write
12
13
14
15
WTR1
RRD
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
RRD
RC
RAS
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-5. DRAMC Time Configuration Register 1 (DRAMC_TC1)
13.3.2.2.3 DRAMC Time Configuration Register 2 (DRAMC_TC2)
Address: Base + 0x000C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
RCD
W
FAW
RTW1
CCD
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
CCD
RTP
RP
RPA
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-6. DRAMC Time Configuration Register 2 (DRAMC_TC2)
The DDR_TIME_CONFIG1 and DDR_TIME_CONFIG2 registers need to be programmed with the
DDR1/DDR2 timing parameters. All times are given in clock cycles.
The timing parameters are conceived so the controller system bus clock cycles match with the JEDEC
DDR2 specification. To interface with DDR1 or Mobile-DDR (LPDDR), some timing parameters need not
be enforced, or are calculated differently. Refer to the DRAM datasheet to determine their value. The
timing parameters need to be programmed in function of this DRAM requirement. Table 13-9 gives the
details.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
13-9