PXD20RM Datasheet, PDF (1197/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Chapter 33
Peripheral Bridge (PBRIDGE)
33.1 Introduction
The PBRIDGE is the interface between the system bus and on-chip peripherals. It has a hard-wired
configuration and cannot be re-configured in software.
33.1.1 Overview
PXD20 devices have one PBRIDGE, which provides an interface between the system bus and all lower
bandwidth peripherals. Accesses that fall within the address space of the PBRIDGE are decoded to provide
individual module selects for peripheral devices on the slave bus interface.
33.1.2 Features
The following list summarizes the key features of the PBRIDGE.
• Supports the slave interface signals. This interface is only meant for slave peripherals.
• Supports 32-bit slave peripherals. (Byte, halfword, and word reads and writes are supported to
each.)
33.2 Functional description
The PBRIDGE serves as an interface between a system bus and the peripheral (slave) bus. It functions as
a protocol translator. Accesses that fall within the address space of the PBRIDGE are decoded to provide
individual module selects for peripheral devices on the slave bus interface.
33.2.1 Access support
Aligned 32-bit word accesses, halfword accesses, and byte accesses are supported for the peripherals.
Peripheral registers must not be misaligned, although no explicit checking is performed by the PBRIDGE.
NOTE
Data accesses that cross a 32-bit boundary are not supported.
33.2.1.1 Peripheral write buffering
Buffered writes are not supported by the PXD20 PBRIDGE.
33.2.1.2 Read cycles
Two-clock read accesses are possible with the PBRIDGE when the requested access size is 32-bits or
smaller, and is not misaligned across a 32-bit boundary.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
33-1