PXD20RM Datasheet, PDF (1565/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

47.3.2 Input Synchronizer
The Synchronizer block (1) captures ITU656 protocol signals from the interface, and synchronizes them
to the IPG_CLK domain.
47.3.3 ITU Decoder
The ITU Decoder block (2) detects the ITU656 timing reference signal (consists of a four-word sequence
in the following format: FF-00-00-XY) and extracts HSYNC, VSYNC, field number signals and video
data from the ITU data stream. The format of active pixel data from the ITU stream is YUV 4:2:2. The
decoder block can directly send out this YUV 4:2:2 data, or interpolate it to YUV 4:4:4 format and send
out. This is determined by the MODE444 field in the SCR register (47.2.3.1/47-5). This bit shall not be set
if the down-scaler is enabled, because the down-scaler works on YUV 4:2:2 data format.
47.3.4 Down Scaling
The Down-scaler block (3) performs down-scaling to the incoming video stream. It’s able to scale down
the input video stream by a fractional scaling ratio up to 1/8. The down-scaler block can be
enabled/disabled by software via the SCALER_EN bit in the SCR register. To use the down-scaler video
data extracted from ITU decoder shall be in YUV 4:2:2 format.
The down-scaler uses a bi-linear filter with simple linear interpolation between the two nearest neighbors,
on both horizontal and vertical direction. Scaling is firstly done on the horizonal direction (called XScale),
and then the vertical direction (called YScale). Different scaling factors are supported on horizonal
direction and vertical direction.
Assuming the scaling factors are (factor_h, factor_v), in theory for every pixel (x, y) of the scaled picture
the coordinates of the corresponding pixel in the incoming picture (x1, y1) can be calculated by
multiplying the coordinates with the scaling factors, say (x1 = x * factor_h, y1 = y * factor_v). Now
because the scaling factors can be fractions, the coordinates (x1, y1) are not integer anymore, they are
fractional values. The scalers use the integer part of (x1, y1) to find the two neighboring pixels from the
incoming picture as input to the filters, and the fractional part to derive the weighting factors for
interpolation.
The scaling factors, (factor_h, factor_v), are both 11 bit with the lower 8 bit as the factional part and the
highest 3 bit the integer part. It’s capable of scaling the input picture by up to 8, in steps of 1/256. It’s by
8 if the factor is programmed as all zeros.
Instead of using multipliers to calculate (x1, y1), two 20-bit phase accumulator is used to step through the
source pixels/or lines, where the lower 8 bit is the fractional part. For every output pixel/or line the phase
adder is added to the accumulator. With the 12 bit integer part of the accumulator, up to 4096 source
pixels/or lines can be supported.
So for each target pixel, the current accumulator position is used to determine how the pixel is going to be
produced. As an example, accumulator value 0x123.3a means the step position is between pixel[0x123]
and pixel[0x124], and the output pixel will be calculated by (pixel[0x124] * (0x100 - 0x3a) + pixel[0x123]
* 0x3a) >> 8. The same concept is used for horizontal and vertical scaling.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
47-17