PXD20RM Datasheet, PDF (1332/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 39-3. SGMCTL Register Description (continued)
Field
Description
11-8 Reserved.
7
TOE
Time Out Enable.
0 Disable Timeout
1 Enable Timeout
6
Wave mode Clock Selection. Select the resample clock as channel clock for all Wave Mode channels.
WAVCLKS 0 Use the individual channel clock.
1 Select the resample clock as channel clock for all channels which are in Wave mode
5-3
Reserved.
2
PWME
PWM Output Select. Select the PWM or I2S output.
0 Select the I2S output
1 Select the PWM output.
1
PWM Channel Select. Select the data source for PWM duty cycle.
PWMCHS 0 Select the output data of Mixer Left as the duty cycle of PWM
1 Select the output data of Mixer Right as the duty cycle of PWM
0
SGM Output Selection. Control separate or mixed “frequency” and “volume” outputs for PWM.
OS
0 Separate outputs.
1 Mixed outputs
39.6.2.2 SGM Configuration Register (SGMCFG)
The SGMCFG register determines the configuration of SGM.
SGM Register Base + 0x0004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R _{ATKF ATKF ATKF ATKF RELF RELF RELF RELF NOP NOP NOP NOP TPCE TPCE TPCE TPCE}
W ^{CH3 CH2 CH1 CH0 CH3 CH2 CH1 CH0 ECH3 ECH2 ECH1 ECH0 CH3 CH2 CH1 CH0}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
R _{RPTE RPTE RPTE RPTE} 0
0
0
0
W ^{CH3 CH2 CH1 CH0}
SFCH3
SFCH2
Reset 0
0
0
0
0
0
0
0
0
0
0
0
Figure 39-3. SGM Configuration Register (SGMCFG)
3
2
SFCH1
0
0
1
0
SFCH0
0
0
39-8
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor