PXD20RM Datasheet, PDF (955/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

26.7.9 Negating an Interrupt Request Outside of its ISR
26.7.9.1 Negating an Interrupt Request as a Side Effect of an ISR
Some peripherals have flag bits that can be cleared as a side effect of servicing a peripheral interrupt
request. For example, reading a specific register can clear the flag bits and their corresponding interrupt
requests. This clearing as a side effect of servicing a peripheral interrupt request can cause the negation of
other peripheral interrupt requests besides the peripheral interrupt request whose ISR presently is
executing. This negating of a peripheral interrupt request outside of its ISR can be a desired effect.
26.7.9.2 Negating Multiple Interrupt Requests in One ISR
An ISR can clear other flag bits besides its own. One reason that an ISR clears multiple flag bits is because
it serviced those flag bits, and therefore the ISRs for these flag bits do not need to be executed.
26.7.9.3 Proper Setting of Interrupt Request Priority
Whether an interrupt request negates outside its own ISR due to the side effect of an ISR execution or the
intentional clearing a flag bit, the priorities of the peripheral or software configurable interrupt requests for
these other flag bits must be selected properly. Their PRIx values in INTC_PSR0_3–INTC_PSR236_238
must be selected to be at or lower than the priority of the ISR that cleared their flag bits. Otherwise, those
flag bits can cause the interrupt request to the processor to assert. Furthermore, the clearing of these other
flag bits also has the same timing relationship to the writing to INTC_SSCIR0_3–INTC_SSCIR4_7 as the
clearing of the flag bit that caused the present ISR to be executed (see Section 26.6.3.1.2, End of Interrupt
Exception Handler).
A flag bit whose enable bit or mask bit negates its peripheral interrupt request can be cleared at any time,
regardless of the peripheral interrupt request’s PRIx value in INTC_PSRx_x.
26.7.10 Examining LIFO contents
In normal mode, the user does not need to know the contents of the LIFO. He may not even know how
deeply the LIFO is nested. However, if he wants to read the contents, such as in debug mode, they are not
memory mapped. The contents can be read by popping the LIFO and reading the PRI field in either
INTC_CPR. The code sequence is:
pop_lifo:
store to INTC_EOIR
load INTC_CPR, examine PRI, and store onto stack
if PRI is not zero or value when interrupts were enabled, branch to pop_lifo
When the examination is complete, the LIFO can be restored using this code sequence:
push_lifo:
load stacked PRI value and store to INTC_CPR
load INTC_IACKR
if stacked PRI values are not depleted, branch to push_lifo
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
26-33