PXD20RM Datasheet, PDF (1077/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 29-6. Mode Enable Register (ME_ME) Field Descriptions (continued)
Field
TEST
RESET
TEST mode enable
0 TEST mode is disabled
1 TEST mode is enabled
RESET mode enable
0 RESET mode is disabled
1 RESET mode is enabled
Description
29.3.2.4 Interrupt Status Register (ME_IS)
Address 0xC3FD_C00C
Access: User read, Supervisor read/write, Test read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
000000000000
W
w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 29-5. Interrupt Status Register (ME_IS)
This register provides the current interrupt status.
Table 29-7. Interrupt Status Register (ME_IS) Field Descriptions
Field
Description
I_ICONF_CU Invalid mode configuration interrupt (Clock Usage) — This bit is set during a mode transition if a clock
which is required to be on by an enabled peripheral is configured to be turned off. It is cleared by
writing a ‘1’ to this bit.
0 No invalid mode configuration (clock usage) interrupt occurred
1 Invalid mode configuration (clock usage) interrupt is pending
I_ICONF
Invalid mode configuration interrupt — This bit is set whenever a write operation to
ME_<mode>_MC registers with invalid mode configuration is attempted. It is cleared by writing a ‘1’
to this bit.
0 No invalid mode configuration interrupt occurred
1 Invalid mode configuration interrupt is pending
I_IMODE
Invalid mode interrupt — This bit is set whenever an invalid mode transition is requested. It is
cleared by writing a ‘1’ to this bit.
0 No invalid mode interrupt occurred
1 Invalid mode interrupt is pending
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
29-19