PXD20RM Datasheet, PDF (1082/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 29-10. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions (continued)
Field
Description
SCSRC_SC
Secondary Clock Sources State Change during mode transition indicator — This bit is set when a
secondary clock source is requested to change its power up/down state. It is cleared when all
secondary system clock sources have completed their state changes. (A ’secondary clock source’ is
a clock source other than FIRC.)
0 No state change is taking place
1 A state change is taking place
SYSCLK_S System Clock Switching pending status —
W
0 No system clock source switching is pending
1 A system clock source switching is pending
CFLASH_SC CFLASH State Change during mode transition indicator — This bit is set when the CFLASH is
requested to change its power up/down state. It is cleared when the DFLASH has completed its state
change.
0 No state change is taking place
1 A state change is taking place
CDP_PRPH
_0_143
Clock Disable Process Pending status for Peripherals 0…143 — This bit is set when any peripheral
has been requested to have its clock disabled. It is cleared when all the peripherals which have been
requested to have their clocks disabled have entered the state in which their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
CDP_PRPH
_96_127
Clock Disable Process Pending status for Peripherals 96…127 — This bit is set when any peripheral
appearing in ME_PS3 has been requested to have its clock disabled. It is cleared when all these
peripherals which have been requested to have their clocks disabled have entered the state in which
their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
CDP_PRPH
_64_95
Clock Disable Process Pending status for Peripherals 64…95 — This bit is set when any peripheral
appearing in ME_PS2 has been requested to have its clock disabled. It is cleared when all these
peripherals which have been requested to have their clocks disabled have entered the state in which
their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
CDP_PRPH
_32_63
Clock Disable Process Pending status for Peripherals 32…63 — This bit is set when any peripheral
appearing in ME_PS1 has been requested to have its clock disabled. It is cleared when all these
peripherals which have been requested to have their clocks disabled have entered the state in which
their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
CDP_PRPH
_0_31
Clock Disable Process Pending status for Peripherals 0…31 — This bit is set when any peripheral
appearing in ME_PS0 has been requested to have its clock disabled. It is cleared when all these
peripherals which have been requested to have their clocks disabled have entered the state in which
their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
29-24
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor