PXD20RM Datasheet, PDF (96/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 3-4. DRAM interface pin summary (continued)
Port pin¹
Function
I/O
direction
Pad
type
PCR
RESET
config²
DDR_A[1]
DRAM address [1]
Output
DDR
PCR[203] Output,
None
DDR_A[0]
DRAM address [0]
Output
DDR
PCR[202] Output,
None
DRAM Bank Address
DDR_BA[2]
DRAM Bank Address[2]
Output
DDR
PCR[220] Output,
None
DDR_BA[1]
DRAM Bank Address[1]
Output
DDR
PCR[219] Output,
None
DDR_BA[0]
DRAM Bank Address[0]
Output
DDR
PCR[218] Output,
None
DRAM Control
DDR_CAS
Column Address Strobe
Output
DDR
PCR[221] Output,
None
DDR_RAS
Row Address Strobe
Output
DDR
PCR[227] Output,
None
DDR_WEB
Write Enable
Output
DDR
PCR[228] Output,
None
DDR_ODT
DRAM On-die termination
Output
DDR
PCR[226] Output,
Pull Down
DDR_CLK
DRAM Clock
Output
DDR
PCR[225] Output,
None
DDR_CLKB DRAM Clock bar
Output
DDR
NA
Output,
None
DDR_CK
DRAM Clock Enable
Output
DDR
PCR[222] Output,
Pull Down
DDR_CS
DRAM Chip Select
Output
DDR
PCR[223] Output,
None
MVREF
DDR Reference Voltage
Input
—
NA
—
MVTT
DRAM Termination Voltage
Input
—
NA
—
1 _{These port pins are disabled and unpowered on packages where the DRAM interface is not bonded out.}
2 _{Reset configuration is given as I/O direction and pull direction (for example, “Input, pullup”).}
Pin number
416 TEPBGA
B10
A10
A9
A8
A7
B6
B7
B9
D5
C7
D7
D8
D9
J4
F2,J2,M2,R2
3.3.7 VIU muxing
The DCU3, DCULite and VIU2 modules share the same pins for input video. It is, however, possibile to
feed independent video streams to VIU2 and DCU3 (operating in narrow mode). Figure 3-4 explains the
pin sharing arrangement.
3-12
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor