PXD20RM Datasheet, PDF (747/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

system clock
input event
internal counter
1
2
3
0
1
2
3
0
1
2
match value = 3
see note 1
FLAG set event
FLAG pin/register
FLAG clear
Note 1: When a match occurs, the first system clock cycle is used to clear the
internal counter, and at the next edge of prescaler clock enable
the counter will start counting.
Figure 18-39. Time base generation with external clock and clear on match start
PRESCALED CLOCK RATIO = 3
system clock
prescaler clock enable
internal counter
1
2
3
0
0
1
2
3
0
0
match value = 3
see note 1
FLAG set event
FLAG pin/register
FLAG clear
Note 1: When a match occurs, the first clock cycle is used to clear the
internal counter, and only after a second edge of pre scaled clock
the counter will start counting.
Figure 18-40. Time base generation with internal clock and clear on match start
PRESCALED CLOCK RATIO = 3
system clock
input event/prescaler clock enable
internal counter
1
2
3
0
1
2
3
0
match value = 3
FLAG set event
see note 1
FLAG pin/register
FLAG clear
Note 1: The match occurs only when the input event/prescaler clock enable is active.
Then, the internal counter is immediately cleared.
Figure 18-41. Time base generation with clear on match end
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
18-45