PXD20RM Datasheet, PDF (291/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

10.7.2 Signal names and descriptions
10.7.2.1 Peripheral Chip Select / Slave Select (CS_0)
In master mode, the CS_0 signal is a peripheral chip select output that selects the slave device to which
the current transmission is intended.
In slave mode, the CS_0 signal is a slave select input signal that allows an SPI master to select the DSPI
as the target for transmission. CS_0 must be configured as input and pulled high. If the internal pullup is
being used then the appropriate bits in the relevant SIU_PCR must be set (SIU_PCR [WPE = 1],
[WPS = 1]).
Set the IBE and OBE bits in the SIU_PCR for all CS_0 pins when the DSPI chip select or slave select
primary function is selected for that pin. When the pin is used for DSPI master mode as a chip select output,
set the OBE bit. When the pin is used in DSPI slave mode as a slave select input, set the IBE bit.
10.7.2.2 Peripheral Chip Selects 1–2 (CS1:2)
CS1:2 are peripheral chip select output signals in master mode. In slave mode these signals are not used.
10.7.2.3 Serial Input (SIN_x)
SIN_x is a serial data input signal.
10.7.2.4 Serial Output (SOUT_x)
SOUT_x is a serial data output signal.
10.7.2.5 Serial Clock (SCK_x)
SCK_x is a serial communication clock signal. In master mode, the DSPI generates the SCK. In slave
mode, SCK_x is an input from an external bus master.
10.8 Memory map and register description
10.8.1 Memory map
Table 10-2 shows the DSPI memory map.
Table 10-2. DSPI detailed memory map
Address
Base:
0xFFF9_0000 (DSPI 0)
0xFFF9_4000 (DSPI 1)
0xFFF9_8000 (DSPI 2)
Base + 0x0004
Register description
DSPI module configuration register (DSPIx_MCR)
Reserved
Location
on page 10-7
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Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
10-5