PXD20RM Datasheet, PDF (198/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

FXOSC_clk
FIRC_clk
FMPLL0_clk/2
(e.g. 125 MHz)
System_clk
RTC/API clock source (rtc_clk)
FMPLL1_clk (undivided)
SIRC_clk (128 KHz undivided)
SXOSC_clk (32 KHz undivided)
CLKOUT
1, 2, 4, 8
Secondary PLL1_clk
FMPLL1
DCULite clock ^{DCULite clock}
selector
VIU_in_clk
PLL0_clk2
DCU3 clock
selector
DCU3 clock
VIU_in_clk
FXOSC_divided
FIRC_divided
Clock
Selector
1 to 16
FXOSC_divided
FIRC_divided
Clock
Selector
1 to 16
DCULite
TCON/
RSDS
DCU3
eMIOS1
(16ch)
eMIOS0
(16ch)
OscA
(XOSC)
IRC
Fast
FXOSC_clk
(e.g. 4 MHz)
FIRC_clk
(e.g. 16 MHz)
1 to 32 ^{FXOSC_clk_divided}
FIRC_divided
1 to 32
System
Clock
Selector
Primary
FMPLL0
PLL0_clk
(e.g. 250 MHz)
2
Clock
Selector
System_clk
Clock Monitor
Unit
FlexCAN
Part of peripheral set
Option to clock from
2
XOSC
or from system clk
Reset / INT
(via MC_RGM)
1 to 16 ^{Serial Interface Clock}
Platform
CPU
GPU
Memories
1 to 16
1 to 16
1 to 16
QuadSPI
DRAM
Controller
Peripheral
Set 1
Peripheral
Set 2
Peripheral
Set 3
ADC
2
Peripheral
Set 4
SGM
OscB ^SXOSC_clk
(XOSC) (32 kHz)
IRC
Slow
SIRC_clk
(128 kHz)
1 to 32 ^{SXOSC_clk_divided}
1 to 32
SIRC_divided
Figure 8-1. PXD20 system clock generation
SXOSC_clk_divided
FXOSC_clk_divided
IRC_fast_divided
SIRC_divided
RTC/API
IRC_slow_undivided _Watchdog
PXD20 Microcontroller Reference Manual, Rev. 1
8-2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice