PXD20RM Datasheet, PDF (717/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Depending on the mode of operation, internal registers B1 or B2 can be assigned to address CBDR[n].
Both B1 and B2 are cleared by reset. Table 18-11 summarizes the CBDR[n] writing and reading accesses
for all operation modes. For more information see section Section 18.7.1.1, UC Modes of Operation.
Table 18-11. CADR[n], CBDR[n] and ALTCADR[n] value assignments
Operation Mode
write
read
Register access
write
read
GPIO
SAIC¹
SAOC¹
MCB¹
A1, A2
A1
B1, B2
B1
—
A2
B2
B2
A2
A1
B2
B2
A2
A1
B2
B2
OPWFMB
A2
A1
B2
B1
OPWMB
QDEC¹
A2
A1
B2
B1
A1
A1
B2
B2
1 _{In these modes, the register CBDR[n] is not used, but B2 can be accessed.}
alt write
A2
—
—
—
—
—
—
alt read
A2
—
—
—
—
—
—
18.6.2.7 eMIOS200 UC Counter Register (CCNTR[n])
address: UC[n] base address + 0x08
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W¹
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CCNTR
W¹
RESET: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or reserved
Figure 18-10. eMIOS200 UC Counter Register (CCNTR[n])
1 _{In GPIO mode or Freeze action, this register is writable.}
The CCNTR[n] contains the value of the internal counter. When GPIO mode is selected or the channel is
frozen, the CCNTR[n] is read/write. For all others modes, the CCNTR[n] is a read-only register. When
entering some operation modes, this register is automatically cleared (refer to Section 18.7.1.1, UC Modes
of Operation, for details).
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
18-15