PXD20RM Datasheet, PDF (857/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

• Prefetched - the buffer contains valid data which has been prefetched to satisfy a potential future
AHB access
• Busy AHB - the buffer is currently being used to satisfy an AHB burst read
• Busy Fill - the buffer has been allocated to receive data from the flash array, and the array access
is still in progress
Selection of a buffer to be loaded on a miss is based on the following replacement algorithm:
1. First, the buffers are examined to determine if there are any invalid buffers. If there are multiple
invalid buffers, the one to be used is selected using a reverse numeric priority, where buffer 0 is
selected first, then buffer 1, etc.
2. If there are no invalid buffers, the least-recently-used buffer is selected for replacement.
Once the candidate line buffer has been selected, the flash array is accessed and read data loaded into the
buffer. If the buffer load was in response to a miss, the just-loaded buffer is immediately marked as
most-recently-used. If the buffer load was in response to a speculative fetch to the next-sequential line
address after a buffer hit, the recently-used status is not changed. Rather, it is marked as
most-recently-used only after a subsequent buffer hit.
This policy maximizes performance based on reference patterns of flash accesses and allows for
prefetched data to remain valid when non-prefetch enabled bus masters are granted flash access.
Several algorithms are available for prefetch control which trade off performance for power. More
aggressive prefetching increases power due to the number of wasted (discarded) prefetches, but may
increase performance by lowering average read latency.
In order for prefetching to occur, PFCRPx[BFEN] must be set to ‘1’; PFCRPx[PFLIM] must be non-zero;
either PFCRPx[IPFEN] or PFCRPx[DPFEN] must be ‘1’ and PFCRPx[MxPFE] must be ‘1’.
21.4.5.2 Instruction / Data Prefetch Triggering
Prefetch triggering may be enabled for instruction reads via the PFCRPx[IPFEN] control bit, while
prefetching for data reads is enabled via the PFCRPx[DPFEN] control bit. Additionally, the
PFCRPx[PFLIM] must also be set to enable prefetching. Prefetches are never triggered by write cycles.
21.4.5.3 Per-Master Prefetch Triggering
Prefetch triggering may be controlled for individual bus masters via the PFCRPx[MxPFE] control
field.
21.4.5.4 Buffer Allocation
Allocation of the line read buffers is controlled via the PFCRPx control register for each AHB port. The
LBCFG field of this register defines the operating organization of the four line buffers. The buffers can be
organized as a “pool” of available resources with all four buffers available for either instruction or data.
They can also be configured with a fixed partition between buffers allocated to instruction or data
accesses. For the fixed partition, two configurations are supported. In one configuration, buffers 0 and 1
are allocated for instruction fetches and buffers 2 and 3 for data accesses. In the second configuration,
buffers 0, 1 and 2 are allocated for instruction fetches and buffer 3 reserved for data accesses. In this con-
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
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