PXD20RM Datasheet, PDF (1222/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 35-7. QSPI_MCR Field Descriptions
Field
Description
D_RSVD Reserved bit.
This bit is writable but should be kept as value 0.
MDIS
Module Disable. The MDIS bit allows the clock to the non-memory mapped logic in the QuadSPI to
be stopped, putting the QuadSPI in a software controlled power-saving state. See Section 35.5.4.2,
Module Disable Mode, for more information.
0 Enable QuadSPI clocks.
1 Allow external logic to disable QuadSPI clocks.
CLR_TXF
Clear TX FIFO/Buffer. Invalidate the TX Buffer content.
0 No action
1 Read and write pointers of the RX Buffer are reset to 0. QSPI_TBSR[TRCTR] is reset to 0.
CLR_RXF
Clear RX FIFO. Invalidate the RX Buffer.
0 No action
1 Read and write pointers of the RX Buffer are reset to 0. QSPI_RBSR[RDBFL] is reset to 0.
VMID
VMID — Vendor Model ID. This field applies to Flash A and Flash B.
0000 Reserved
0001 Winbond
0010 Spansion
0011 Macronix
0100 Numonyx
others Reserved
EXT_ADD¹ Extended memory address modes.
0 Default mode, 24-bit addressing.
1 32-bit addressing.
1 _{This bit is set to enable the QSPI for 32-bit addressing mode. The respective external serial flash memory should}
also be independently enabled for accepting 32-bit addresses.
35.4.4.3 Latency Configuration Register (QSPI_LCR)
The Latency Configuration Register is used to insert a variable number of dummy cycles during command
execution. The dummy cycle insertion is dependent on memory vendor (refer to vendor’s memory
specification guide), frequency of serial flash clock (SCK) and type of command (refer to QSPI latency
support, Table 35-9).
35-12
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor