PXD20RM Datasheet, PDF (976/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 27-6. BDRL access in UART mode (continued)
Access
Mode¹
Word length²
IPS operation result
Read Byte0-1-2-3
FIFO
Byte/Half-word
IPS transfer error
Read Half-word0-1
FIFO
Byte/Half-word
IPS transfer error
Read Word
FIFO
Byte/Half-word
IPS transfer error
Write Byte0-1-2-3
BUFFER
Byte/Half-word
OK
Write Half-word0-1
BUFFER
Byte/Half-word
OK
Write Word
BUFFER
Byte/Half-word
OK
Read Byte0-1-2-3
BUFFER
Byte/Half-word
OK
Read Half-word0-1
BUFFER
Byte/Half-word
OK
Read Word
BUFFER
Byte/Half-word
OK
NOTES:
1 _{As specified by UARTCR[TFBM]}
2 _{As specified by the WL1 and WL0 bits of the UARTCR register. In UART FIFO mode (UARTCR[TFBM] = 1),any}
read operation causes an IPS transfer error.
27.9.4 UART receiver
Reception of a data byte is started as soon as the software completes the following tasks in order:
1. Exits Initialization mode
2. Sets the UARTCR[RXEN] field
3. Detects the start bit
There is a dedicated data buffer for received data bytes. Its size is as follows:
• 4 bytes when UARTCR[WL1] = 0
• 2 half-words when UARTCR[WL1] = 1
After the programmed number (RDFL bits) of bytes has been received, the UARTSR[DRFRFE] field is
set. If the UARTCR[RXEN] field is cleared during a reception, the current reception is completed, but no
further reception can be invoked until UARTCR[RXEN] is set again.
The buffer can be configured in FIFO mode (required when DMA Rx is enabled) by setting
UARTCR[RFBM].
The access to the BDRM register is shown in Table 27-7.
Table 27-7. BDRM access in UART mode
Access
Mode¹
Word length²
IPS operation result
Read Byte4
Read Byte5-6-7
Read Half-word2-3
Read Word
FIFO
FIFO
FIFO
FIFO
Byte
Byte
Byte
Byte
OK
IPS transfer error
IPS transfer error
IPS transfer error
27-20
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor