PXD20RM Datasheet, PDF (873/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 22-12. Color Depth Conversion mapping (MODE[0] = 1)
Offset
64-bit GFX2D Data
Address [7:0] [15:8 [23:1 [31:2 [39:3 [47:4 [55:4 [63:5
] 6] 4] 2] 0] 8] 6]
—
—
0x30 ^A12 ^R12 ^G12 ^B12 ^A13 ^R13 ^G13 ^B13
0x38 ^A14 ^R14 ^G14 ^B14 ^A15 ^R15 ^G15 ^B15
0x40 ^A16 ^R16 ^G16 ^B16 ^A17 ^R17 ^G17 ^B17
0x48 ^A18 ^R18 ^G18 ^B18 ^A19 ^R19 ^G19 ^B19
—
—
0x80 ^A32 ^R32 ^G32 ^B32 ^A33 ^R33 ^G33 ^B33
0x88 ^A34 ^R34 ^G34 ^B34 ^A35 ^R35 ^G35 ^B35
0x90 ^A36 ^R36 ^G36 ^B36 ^A37 ^R37 ^G37 ^B37
0x98 ^A38 ^R38 ^G38 ^B38 ^A39 ^R39 ^G39 ^B39
—
—
0xB0 ^A44 ^R44 ^G44 ^B44 ^A45 ^R45 ^G45 ^B45
0xB8 ^A46 ^R46 ^G46 ^B46 ^A47 ^R47 ^G47 ^B47
0xC0 ^A48 ^R48 ^G48 ^B48 ^A49 ^R49 ^G49 ^B49
0xC8 ^A50 ^R50 ^G50 ^B50 ^A51 ^R51 ^G51 ^B51
Offset
64-bit Physical RAM Data
Address [7:0] [15:8 [23:1 [31:2 [39:3 [47:4 [55:4 [63:5
] 6] 4] 2] 0] 8] 6]
—
—
0x20 ^B10 ^R11 ^G11 ^B11 ^R12 ^G12 ^B12 ^R13
0x28 ^G13 ^B13 ^R14 ^G14 ^B14 ^R15 ^G15 ^B15
0x30 ^R16 ^G16 ^B16 ^R17 ^G17 ^B17 ^R18 ^G18
0x38 ^B18 ^R19 ^G19 ^B19 ^R20 ^G20 ^B20 ^R21
—
—
0x60 ^R32 ^G32 ^B32 ^R33 ^G33 ^B33 ^R34 ^G34
0x68 ^B34 ^R35 ^G35 ^B35 ^R36 ^G36 ^B36 ^R37
0x70 ^G37 ^B37 ^R38 ^G38 ^B38 ^R39 ^G39 ^B39
0x78 ^R40 ^G40 ^B40 ^R41 ^G41 ^B41 ^R42 ^G42
—
—
0x80 ^B42 ^R43 ^G43 ^B43 ^R44 ^G44 ^B44 ^R45
0x88 ^G45 ^B45 ^R46 ^G46 ^B46 ^R47 ^G47 ^B47
0x90 ^R48 ^G48 ^B48 ^R49 ^G49 ^B49 ^R50 ^G50
0x98 ^B50 ^R51 ^G51 ^B51 ^R52 ^G52 ^B52 ^R53
22.4.7 Alpha buffer write suppressor
Certain graphic accelerator operations may perform redundant memory writes. This particularly applies to
alpha buffer operations. To save space in RAM, each GXG window can suppress writes into memory at
addresses specified in the window. In addition reads from this window will be replaced with a fixed "alpha"
value.
Program this mode by selecting the value 1 for the value of MODE in the window configuration register.
The fixed "alpha" value is provided by the ALPHA bit-field in the same register.
22.4.8 Serial flash exclusive access
The GXG is configured to use the Exclusive Access capability of the QuadSPI module. This is provided
to avoid the situation where a graphic operation is underway and another master requests a different
QuadSPI operation thus disrupting the flow of data to the GXG. If a graphic operation requires access to
the QuadSPI then the GXG will suspend operations until the QuadSPI modules grants exclusive access.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
22-13