PXD20RM Datasheet, PDF (1234/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Address: QSPI_BASE + 0x164
Write: Anytime
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
R0 0 0 0
0000
000
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0
0
0
000
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 35-15. Interrupt and DMA Request Select and Enable Register (QSPI_SFMRSER)
Table 35-21. QSPI_SFMRSER Field Descriptions
Field
TBFIE
TBUIE
RBDDE
RBOIE
RBDIE
ABCEIE
ABMEIE
ABOIE
IUEIE
ICEIE
IMEIE
IPAEIE
IPIEIE
IPGEIE
TFIE
Description
TX Buffer Fill Interrupt Enable
TX Buffer Underrun Interrupt Enable
RX Buffer Drain DMA Enable: Enables generation of DMA requests for RX Buffer Drain. When
this bit is set DMA requests via the ipd_req_rfdf line are generated as long as the
QSPI_SFMSR[RXWE] status bit is set.
0 No DMA request will be generated
1 DMA request will be generated
RX Buffer Overflow Interrupt Enable
RX Buffer Drain Interrupt Enable: Enables generation of IRQ requests for RX Buffer Drain. When
this bit is set the ipi_int_rfdf line is asserted as long as the QSPI_SFMSR[RBDF] flag is set.
0 No RBDF interrupt will be generated
1 RBDF Interrupt will be generated
AHB Command Error Interrupt Enable
AHB Mode Error Interrupt Enable
AHB Buffer Overflow Interrupt Enable
IP Command Usage Error Interrupt Enable
IP Command Error Interrupt Enable
IP Command Mode Error Interrupt Enable
IP Command Trigger during AHB Access Error Interrupt Enable
IP Command Trigger during IP Access Error Interrupt Enable
IP Command Trigger during AHB Grant Error Interrupt Enable
Transaction Finished Interrupt Enable
35-24
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor