PXD20RM Datasheet, PDF (1045/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 28-2. MPU_CESR field descriptions
Field
NRGD
VLD
Description
Number of Region Descriptors. This 4-bit read-only field specifies the number of region descriptors
implemented in the MPU. The defined encodings include:
0000 8 region descriptors
0001 12 region descriptors
0010 16 region descriptors (the number of descriptors on the PXD20)
Valid. This bit provides a global enable/disable for the MPU.
0 The MPU is disabled.
1 The MPU is enabled.
While the MPU is disabled, all accesses from all bus masters are allowed.
28.2.2.2 MPU Error Address Register, Slave Port n (MPU_EARn)
When the MPU detects an access error on slave port n, the 32-bit reference address is captured in this
read-only register and the corresponding bit in the MPU_CESR[SPERR] field set. Additional information
about the faulting access is captured in the corresponding MPU_EDRn register at the same time. Note this
register and the corresponding MPU_EDRn register contain the most recent access error; there are no
hardware interlocks with the MPU_CESR[SPERR] field as the error registers are always loaded upon the
occurrence of each protection violation.
Offset MPU_Base + 0x010 (MPU_EAR0)
MPU_Base + 0x018 (MPU_EAR1)
MPU_Base + 0x020 (MPU_EAR2)
MPU_Base + 0x028 (MPU_EAR3)
Access: Read
Read
Read
Read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
EADDR
W
Reset _{- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -}
Figure 28-3. MPU Error Address Register, Slave Port n (MPU_EARn)
Table 28-3. MPU_EARn Field Descriptions
Field
Description
EADDR Error Address. This read-only field is the reference address from slave port n that generated the access
error.
28.2.2.3 MPU Error Detail Register, Slave Port n (MPU_EDRn)
When the MPU detects an access error on slave port n, 32 bits of error detail are captured in this read-only
register and the corresponding bit in the MPU_CESR[SPERR] field set. Information on the faulting
address is captured in the corresponding MPU_EARn register at the same time. Note this register and the
corresponding MPU_EARn register contain the most recent access error; there are no hardware interlocks
with the MPU_CESR[SPERR] field as the error registers are always loaded upon the occurrence of each
protection violation.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
28-7