PXD20RM Datasheet, PDF (762/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Register address: ECSM Base + 0x65
0
1
2
3
4
5
6
7
R
RESR[0:7]
W
RESET:
x
x
x
x
x
x
x
x
= Unimplemented
Figure 19-10. RAM ECC Syndrome (RESR) Register
Table 19-11. RAM ECC Syndrome (RESR) Field Descriptions
Name
Description
0-7
RESR[0:7]
RAM ECC Syndrome Register
This 8-bit syndrome field includes 6 bits of Hamming decoded parity plus an odd-parity bit for the entire
39-bit (32-bit data + 7 ECC) code word. The upper 7 bits of the syndrome specify the exact bit position
in error for single-bit correctable codewords, and the combination of a non-zero 7-bit syndrome plus
overall incorrect parity bit signal a multi-bit, non-correctable error.
For correctable single-bit errors, the mapping shown in Table 19-11 associates the upper 7 bits of the
syndrome with the data bit in error.
Note: Table 19-11 associates the upper 7 bits of the ECC syndrome with the exact data bit in error for single-bit correctable
codewords. This table follows the bit vectoring notation where the LSB=0. Note that the syndrome value of 0x01 implies
no error condition but this value is not readable when the PRESR is read for the no error case.
Table 19-12. RAM Syndrome Mapping for Single-Bit Correctable Errors
RESR[0:7]
0x00
0x01
0x02
0x04
0x06
0x08
0x0a
0x0c
0x0e
0x10
0x12
0x14
0x16
0x18
0x1a
0x1c
0x50
0x20
0x22
Data Bit in Error
ECC ODD[0]
No Error
ECC ODD[1]
ECC ODD[2]
DATA ODD BANK[31]
ECC ODD[3]
DATA ODD BANK[30]
DATA ODD BANK[29]
DATA ODD BANK[28]
ECC ODD[4]
DATA ODD BANK[27]
DATA ODD BANK[26]
DATA ODD BANK[25]
DATA ODD BANK[24]
DATA ODD BANK[23]
DATA ODD BANK[22]
DATA ODD BANK[21]
ECC ODD[5]
DATA ODD BANK[20]
19-14
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor