PXD20RM Datasheet, PDF (220/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

16 MHz int. RC osc.
div. 4-16 MHz ext. xtal osc.
primary PLL/2
system clock is disabled if
0 _{ME_<current mode>_MC.SYSCLK = “1111”}
3
4
‘0’
system clock
MC_RGM SAFE mode request
“0000” 1
ME_<current mode> ₀
_MC.SYSCLK
CGM_SC_SS Register
CGM_SC_DC0 Register
clock divider
peripheral set 1 clock
CGM_SC_DC1 Register
clock divider
peripheral set 2 clock
CGM_SC_DC2 Register
clock divider
peripheral set 3 clock

peripheral set 4 clock
Figure 8-18.
Figure 8-19. MC_CGM system clock generation overview
8.3.4.1.1 System clock source selection
During normal operation, the system clock selection is controlled
• On a SAFE mode or reset event, by the MC_RGM
• Otherwise, by the MC_ME
8-24
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor