PXD20RM Datasheet, PDF (1609/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

50.5 Peripherals and general application guidelines
Optimizing the device configuration and compiler setup is only one part of optimizing an entire
application. Correct use of the peripherals can also dramatically improve overall system performance. In
particular, use of the interrupt controller,and the enhanced Direct Memory Access (eDMA), can off-load
significant work from the e200z4d.
For example, eDMA may be used to shift data to avoid unnecessary CPU loading. Most peripheral
modules can generate eDMA requests to trigger data transfers. An example of a typical application is to
use the eDMA to move CAN messages from one FlexCAN module to another.
Section 50.6, Performance optimization checklist, provides several system level examples of how to
optimize an application.
50.6 Performance optimization checklist
Table 50-5. Performance optimization checklist—Part 1. Hardware configuration
Description
Branch Target Buffer
Branch Prediction
System Frequency
Register(s)
Flush with BUCSR[BBFI]
Enable with BUCSR[BPEN]
BUCSR[BPRED]/HID0[BPRED]
BUCSR[BALLOC]
FMPLL_CR
FMPLL_MR
Flash Wait States
FPCR0[APC, WWSC, RWSC]
Flash Prefetching
FPCR[DPFEN, IPFEN, PFLIM, BFEN]
Flash Prefetch
Algorithm
Crossbar Switch
FPCR[BCFG]
SGPCRn and MPRn
Cache
Invalidate Icache with L1CSR1[ICINV]
Enable Icache with L1CSR1[ICE]
Memory Management TLB_MAS2[VLE, I]
Unit
DRAMC Priority
Manager
MLUTn and associated configuration
registers
Details
Flush and enable to improve accuracy of
branch predictions.
Consider fine tuning of BTB operation for
specific applications.
Select desired frequency and frequency
modulation taking into account the
performance impact of additional wait states.
Refer to Flash chapter Section 21.3.2.8,
Platform Flash Configuration Registers
(PFCRP0 and PFCRP1), for FPCR settings for
FMPLL frequency ranges.
Enable prefetching for instructions. Prefetching
for data should be assessed for the specific
application.
Allocate buffers to data and/or instructions.
Fine tune for specific applications.
Configure ports according to most likely master
to access a slave. In single core designs assign
the e200z4d data port to the second flash port.
In multi-core designs prioritise the flash and
RAM ports to the heaviest users
Invalidate and the enable the cache for
instructions.
Configure relevant pages for cache and VLE by
setting MMU TLB attributes.
Configure the priority manager such that core
cache misses or GFX2D requests escalate
quickly
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
50-11