PXD20RM Datasheet, PDF (1605/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

50.3.6 Memory management unit (MMU)
50.3.6.1 Description
The Memory Management Unit is a 32-bit Power Architecture compliant implementation which provides
functionality that includes address translation and application of access attributes to memory ranges
defined in Translation Lookaside Buffer entries. Although the MMU does not directly impact
performance, it is within the MMU that memory regions are configured to permit the use of system cache
to improve performance and Variable Length Encoding (VLE) to enhance code density. Thus it is essential
that the MMU is correctly configured to ensure optimal application performance is achieved.
50.3.6.1.1 Recommended configuration
The core uses MMU Assist Registers (MASx) which are special purpose registers to facilitate reading,
writing and searching the Translation Lookaside Buffer (TLB) entries. These MAS registers are software
managed by tlbre, tlbwe, tlbsx, tlbsync, and tlbivax instructions. Refer to the core reference manual for
full details of the MMU and its configurations.
There are several MMU Assist Register registers (MAS0–3) that require configuring. Details of these are
provided in the e200z4d reference manual. Specifically, the MAS2 register contains the fields to control
whether a specified memory region described by the valid TLB Entry is cache inhibited or whether VLE
encoding is valid.
EPN
0
W I MGE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 626; Read/Write
Figure 50-3. MMU Assist Register 2 (MAS2)
Table 50-3. MAS2 field descriptions
Field
EPN
VLE
W
I
M
G
E
Description
Effective page number [0:21]
VLE
0: This page is a standard BookE page
1: This page is a VLE page
Write-through required
Cache inhibited
0: This page is considered cacheable
1: This page is considered cache-inhibited
Memory coherence required
Memory coherence required
Endianness
Refer to the e200z4d core reference manual for further details of MMU configuration registers.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
50-7