PXD20RM Datasheet, PDF (1140/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 31-9. Clock Enable (G12_CLOCKEN) Field Description
Field
31–6
5–3
2
1
0
Reserved
Legacy
Enable VG level 1 and level 2 clock
Enable 2D and VG level 3 clock
Enable burst cache clock
Description
31.3.9 MMU_READ_ADDR
Offset 0x510
Access: User write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
ADDR
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 31-10. MMU Read Address (MMU_READ_ADDR)
Table 31-10. MMU Read Address (MMU_READ_ADDR) Field Descriptions
Field
31–15 Reserved
14–0 Register Address
Description
31.3.10 MMU_READ_DATA
Offset 0x518
Access: User read
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 31-11. MMU Read Data (MMU_READ_DATA)
Table 31-11. MMU Read Data (MMU_READ_DATA) Field Descriptions
Field
Description
31–0 Register Data
31-8
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor