PXD20RM Datasheet, PDF (164/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 5-17. Injected Conversion Mask Registers (JCMR[1..2]) field descriptions
Field
31
n
Description
CH0: Sampling enable
When set, sampling is enabled for channel 0.
CHn: Sampling enable
When set, sampling is enabled for channel n.
5.3.8 Delay registers
5.3.8.1 Decode Signals Delay Register (DSDR)
Reset value: 0x0000_0000
Address: Base + 0x00C4
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0 0 0 0 0 0 0 0
DSD[0:7]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 5-22. Decode Signals Delay Register (DSDR)
Table 5-18. Decode Signals Delay Register (DSDR) field descriptions
Field
0:23
24:31
Description
Reserved
Write of any value has no effect, read value is always 0.
DSD[0:7]: The delay between the external decode signals and the start of the sampling phase. It is used
to take into account the settling time of the external multiplexer.
The decode signal delay is calculated as: DSD × 1/frequency of ADC clock.
Note: When ADC clock = Peripheral Clock/2, the DSD should be incremented by 2, to see an additional
ADC clock cycle delay on the decode signal.
For example:
DSD = 0; 0 ADC clock cycle delay
DSD = 2; 1 ADC clock cycle delay
DSD = 4; 2 ADC clock cycles delay
5.3.8.2 Power-down Exit Delay Register (PDEDR)
Reset value: 0x0000_0000
5-22
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor