PXD20RM Datasheet, PDF (1600/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Further factors that impact the overall application performance are the use of the intelligent peripherals:
• Use of DMA rather than CPU to transfer data efficiently
• Use of DMA service requests rather than CPU interrupts to avoid software polling
• Off-loading tasks from the CPU to the eDMA
• Careful allocation of cache usage for code ranges.
Different items in this list will have different performance impacts in a real system. Features like the
crossbar switch, system cache, the FMPLL and the flash access times tend to provide the most significant
performance impacts in terms of hardware settings.
The subsequent sections in this chapter describe how to configure and use these features.
50.3 Configuring hardware features
50.3.1 Branch target buffer (BTB)
50.3.1.1 Description
To resolve branch instructions and improve the accuracy of branch predictions the e200z4d core
implements a dynamic branch prediction mechanism using a branch target buffer (BTB), a fully
associative address cache of branch target addresses. Its purpose is to accelerate the execution of software
loops with some potential change of flow within the loop body. In addition, the BTB on the e200z4d has
a subroutine call stack that speeds up indirect branches.
50.3.1.2 Recommended configuration
By default, the BTB is disabled following reset onthe e200z4d. It is controlled by the Branch Unit Control
and Status Register (BUCSR). The BTB’s contents should be flushed and invalidated by writing
BUCSR[BBFI] = 1, and it may be enabled by subsequently writing BUCSR[BPEN] = 1.
Additional control is available by configuring BUCSR[BPRED] and BUCSR[BALLOC] to control
whether forward or backward branches (or both) are candidates for entry into the BTB, and thus for branch
prediction. By default the BUCSR[BPRED] and BUCSR[BALLOC] fields are set to 0b00, which enables
forward and backward branch prediction. It is recommended to not disable branch prediction although for
extremely fine tuning of a given application the optimum setting of BUCSR[BPRED] and
BUCSR[BALLOC] should be assessed.
0
0
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 1013; Read/Write; Reset - 0x0
Figure 50-1. Branch Unit Control and Status Register (BUCSR)
50-2
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor