PXD20RM Datasheet, PDF (452/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

pdi_clk
RGB565 Narrow Mode (Pdi_clk = 64 MHz Max) LSB transferred first
pdi_data [7:0]
pdi_clk
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
RGB565 Narrow Mode (Pdi_clk = 64 MHz Max) MSB transferred first
pdi_data [7:0]
0x01 0x00 0x03 0x02 0x05 0x04 0x07 0x06 0x09 0x08 0x0B 0x0A 0x0D 0x0C 0x0F 0x0E
RGB565 Normal Mode (Pdi_clk = 64 MHz Max) LSB
pdi_data [15:0] 0x0100 0x0302
0x0504 0x0706
0x0908 0x0B0A 0x0D0C
0x0F0E
Figure 11-93. Data Transfer in Normal and Narrow Mode
The byte transferred first (MSB or LSB) depends on the configuration register as shown in
Figure 11-93.This does not affect the sync preamble sequence in case internal sync mode.
On this device, the incoming RGB data is mapped onto the PDI pins as described in Table 11-78.
Table 11-78. Mapping of RGB data onto PDI pins
Mode
Normal (full 18-bit PDI interface)
Normal (RGB565 16-bit PDI interface)
Narrow (8-bit PDI interface)
Mapping
PDI[17:12] = DCU3_R[5:0]
PDI[11:6] = DCU3_G[5:0]
PDI[5:0] = DCU3_B[5:0]
PDI[15:11] = DCU3_R[4:0]
PDI[[10:5] = DCU3_G[5:0]
PDI[4:0] = DCU3_B[4:0]
RGB565:
In first clock cycle, PDI[7:0] = { DCU3_R[4:0], DCU3_G[5:3] }
In second clock cycle, PDI[7:0] = { DCU3_G[2:0], DCU3_B[4:0] }
YCbCr:
In first clock cycle, PDI[7:0] = { DCU3_Cb[7:0] }
In second clock cycle, PDI[7:0] = { DCU3_Y0[7:0] }
In third clock cycle, PDI[7:0] = { DCU3_Cr[7:0] }
In forth clock cycle, PDI[7:0] = { DCU3_Y1[7:0] }
11-118
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor