PXD20RM Datasheet, PDF (584/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

13.3.2 Register descriptions
13.3.2.1 DRAMC System Configuration Register (DRAMC_SCR)
Address: Base + 0x0000
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
W ^RST
CKE
CLK
ON
CMD
ROW_SEL
BK_SEL
0
0
0
B16
Reset 0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
RDLY[2:0]
WDLY[2:0]
EODT ODT
0
0
W
w1c w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-2. DRAMC System Configuration Register (DRAMC_SCR)
Table 13-2. DRAMC_SCR field descriptions
Field
RST
CKE
CLKON
CMD
ROWSEL
BK_SEL
B16
RDLY[3:0]
Description
DRAMC soft reset. When this bit is 0, the DRAMC is in the reset state. When this bit is 1, the DRAMC
is out of reset. The bit controls the reset to the internal state machines. The configuration registers
are reset by the resets from the hardware reset block, not by this bit.
Value on the DRAM CKE pin. For functional operation, this needs to be high. During power-down,
value can be low.
When this bit is 1, the DRAM clock is running. When this bit is 0, the DRAM clock is stopped
When this bit is 0, the DRAMC is in normal operation. When this bit is 1, the DRAMC is in command
mode and does not respond to requests on the incoming buses. Command mode is used for DRAM
initialization and to switch the DRAM into and out of the different power-down and self-refresh
modes.
These fields control the multiplexing of the bus address to the DRAM bank and row address.
Table 13-5 gives the details. DRAM column address depends on 16-bit mode bit, and relationship is
given in Table 13-5.
When this bit is set, the DRAMC assumes a 16-bit wide memory is used. When this bit is cleared, a
32-bit wide memory is assumed.
Note: This does not configure the pins for 16-bit mode. That must be done in the pin configuration.
This field controls the expected delay between sending a read command to the DRAM and receiving
the read data from the DRAM.
RDLY, HALF DQS DLY, and QUART DQS delay together to code for t_DQSEN.
The t_DQSEN is the delay between the read command and when the internal DQS enable goes high.
See Figure 13-3. Timing is internally compensated, and is referred to timing at the device pins.
t_DQSEN should be selected so the L-H transition of DQS enable is always in the preamble of the DQS
input of the READ command. Required t_DQSEN value depends on the CAS latency (CL), the distance
between the DRAM and the device, and the type of DRAM used. Table 13-3 gives the detail on
programming t_DQSEN.
13-4
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor