PXD20RM Datasheet, PDF (1233/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 35-20. QSPI_SFMFR Field Descriptions (continued)
Field
Description
IMEF
IP Command Mode Error Flag: Set when the execution of a valid IP Command is started and one of
the following condition occurs:
• Mode Bit Collision² is detected
• Mode Bit Error³ is detected.
No communication with the serial flash device is initiated by the QuadSPI module.
Command Arbitration and Execution Related Flags
IPAEF
IP Command Trigger during AHB Access Error Flag. Set when the following condition occurs:
• A write access occurs to the QSPI_ICR[IC] field and the QSPI_SFMFR[AHB_ACC] bit is set. Any
command leading to the assertion of the IPAEF flag is ignored
IPIEF
IP Command Trigger could not be executed Error Flag. Set when the QSPI_SFMSR[IP_ACC] bit is
set and any of the following conditions occurs:
• Write access to the QSPI_ICR register. Any command leading to the assertion of the IPIEF flag is
ignored
• Write access to the QSPI_SFAR register.
• Write access to the QSPI_RBCT register.
IPGEF
IP Command Trigger during AHB Grant Error Flag: Set when the following condition occurs:
• A write access occurs to the QSPI_ICR[IC] field and the QSPI_SFMSR[AHBGNT] bit is set. Any
command leading to the assertion of the IPGEF flag is ignored
TFF
IP Command Transaction Finished Flag: Set when the QuadSPI module has finished a running IP
Command. If an error occurred the related error flags are valid at the latest in the same clock cycle
when the TFF flag is asserted.
1 _{Invalid AHB Command means that the QSPI_ACR[ARIC] field is programmed to a command not reflecting data}
read. Refer to Table 35-43 and Table 35-47 for the related commands.
2 _{Refer to Section 35.6.6, Continuous Mode Commands, for the description of a Mode Bit Collision.}
3 _{When two serial flash devices are accessed simultaneously in Parallel Flash Mode both of the related Continuous}
Mode bits QSPI_SFMSR[CNTMDFA] and QSPI_SFMSR[CNTMDFB] must match with the command. If this is not
the case a Mode Bit Error is detected.
Additional details about the error flags contained in that register can be found in Table 35-35.
35.4.4.14 Interrupt and DMA Request Select and Enable Register
(QSPI_SFMRSER)
The QSPI_SFMRSER register provides enables and selectors for the interrupts in the QuadSPI module.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
35-23