PXD20RM Datasheet, PDF (977/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 27-7. BDRM access in UART mode (continued)
Access
Mode¹
Word length²
IPS operation result
Read Byte4-5-6-7
FIFO
Half-word
Read Half-word2
FIFO
Half-word
Read Half-word3
FIFO
Half-word
Read Word
FIFO
Half-word
Write Byte4-5-6-7
FIFO
Byte/Half-word
Write Half-word2-3
FIFO
Byte/Half-word
Write Word
FIFO
Byte/Half-word
Read Byte4-5-6-7
BUFFER
Byte/Half-word
Read Half-word2-3
BUFFER
Byte/Half-word
Read Word
BUFFER
Byte/Half-word
Write Byte4-5-6-7
BUFFER
Byte/Half-word
Write Half-word2-3
BUFFER
Byte/Half-word
Write Word
BUFFER
Byte/Half-word
NOTES:
1 _{As specified by UARTCR[RFBM]}
2 _{As specified by the WL1 and WL0 bits of the UARTCR register}
IPS transfer error
OK
IPS transfer error
IPS transfer error
IPS transfer error
IPS transfer error
IPS transfer error
OK
OK
OK
IPS transfer error
IPS transfer error
IPS transfer error
Table 27-8 lists some common scenarios, controller responses, and suggestions when the LINFlexD
controller is acting as a UART receiver.
Table 27-8. UART receiver scenarios
Scenario
Responses and suggestions
The software does not know (in advance) how many
bytes will be received.
Do not program UARTCR[RDFLRFC] in advance. When
this field is zero (as it is after reset), reception occurs on
a byte-by-byte basis. Therefore, the state machine will
move to IDLE state after each byte is received.
UARTCR[RDFLRFC] is programmed for a certain
The reception will hang. In this case, the software must
number of bytes received, but the actual number of bytes monitor the UARTSR[TO] field, and move to IDLE state
received is smaller.
by setting LINCR1[SLEEP].
A STOP request arrives before the reception is
completed.
The request is acknowledged only after the programmed
number of data bytes are received. In other words, the
STOP request is not serviced immediately. In this case,
the software must monitor the UARTSR[TO] field and
move the state machine to IDLE state as appropriate. The
stop request will be serviced only after this is complete.
A parity error occurs during the reception of a byte.
The corresponding UARTSR[PEn] field is set. No
interrupt is generated.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
27-21