PXD20RM Datasheet, PDF (850/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

NOTE
Lock and Select are independent. If a block is selected and locked, no erase
occurs.
3. Write to any address in flash. This is referred to as an erase interlock write. The interlock write
causes the values of SOC specific shadow enable to be captured and causing MCR[PEAS] to be
set/cleared.
4. Write a logic 1 to the MCR[EHV] bit to start an internal erase sequence or skip to step 9 to
terminate.
5. Wait until the MCR[DONE] bit goes high.
6. Confirm MCR[PEG] = 1.
7. Write a logic 0 to the MCR[EHV] bit.
8. If more blocks are to be erased, return to step 2.
9. Write a logic 0 to the MCR[ERS] bit to terminate the erase.
The erase sequence is presented graphically in Figure 21-29. The erase suspend operation detailed in
Figure 21-29 is discussed in section Section 21.4.1.3.2, Erase Suspend/Resume.
After setting ERS, one write, referred to as an interlock write, must be performed before EHV can be set
to a 1. This interlock causes the values of SOC specific shadow enable to be captured. Data words written
during erase sequence interlock writes are ignored. The user may terminate the erase sequence by clearing
ERS before setting EHV.
An erase operation may be aborted by clearing EHV assuming DONE is low, EHV is high and ESUS is
low. An erase abort forces the module to step 8 of the erase sequence. An aborted erase results in PEG
being set low, indicating a failed operation. The block(s) being operated on before the abort contain
indeterminate data. The user may not abort an erase sequence while in erase suspend.
WARNING
Aborting an erase operation leaves the FC blocks being erased in an
indeterminate data state. This may be recovered by executing an erase on the
affected blocks.
21-38
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor