PXD20RM Datasheet, PDF (1331/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

SGM Register Base + 0x0000
31
30
29
28
27
26
25
24
23
22
21
20
R _{SOG SOG SOG SOG} 0
W ^{CH3 CH2 CH1 CH0}
0
0
0
0
MDIS
0
0
Reset 0
0
0
0
0
0
0
0
1
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
R _{MOD MOD MOD MOD} 0
W ^{CH3 CH2 CH1 CH0}
0
0
0
TOE
WAV
CLKS
0
0
Reset 0
0
0
0
0
0
0
0
0
1
0
0
Figure 39-2. SGM Control Register (SGMCTL)
19
18
17
16
0
0
0
0
0
0
0
0
3
2
1
0
0
PWM PWM
E CHS
OS
0
0
0
0
Table 39-3. SGMCTL Register Description
Field
Description
31
SOGCH3
30
SOGCH2
29
SOGCH1
28
SOGCH0
27-24
23
MDIS
22-16
15
MODCH3
14
MODCH2
13
MODCH1
12
MODCH0
Start Of Generation of Channel 3. Control the start/Stop of the Channel 3.
0 Stop the channel sound generation.
1 Start the channel sound generation.
Start Of Generation of Channel 2. Control the start/Stop of the Channel 2.
0 Stop the channel sound generation.
1 Start the channel sound generation.
Start Of Generation of Channel 1. Control the start/Stop of the Channel 1.
0 Stop the channel sound generation.
1 Start the channel sound generation.
Start Of Generation of Channel 0. Control the start/Stop of the Channel 0.
0 Stop the channel sound generation.
1 Start the channel sound generation.
Reserved.
Module Disable. Force the SGM into a power-down mode by disabling the module clock.
0 Clock input switched on.
1 Clock input switched off. Force SGM enter low-power.
Note: To enable the SGM, this bit needs to be cleared before configuring other registers of SGM.
Reserved.
Channel 3 mode Selection.
0 Wave mode
1 DDS mode
Channel 2 mode Selection.
0 Wave mode
1 DDS mode
Channel 1 mode Selection.
0 Wave mode
1 DDS mode
Channel 0 mode Selection.
0 Wave mode
1 DDS mode
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
39-7