PXD20RM Datasheet, PDF (362/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Field
12–15
BPP
16
RLE_EN
17–27
LUOFFS
29
BB
30–31
AB
Table 11-9. CtrlDescL0_4 field descriptions (continued)
Description
Bits Per Pixel
4’b0000 = 1 bpp
4’b0001 = 2 bpp
4’b0010 = 4 bpp
4’b0011 = 8 bpp
4’b0100 = 16 bpp (RGB565)
4’b0101 = 24 bpp
4’b0110 = 32 bpp (BGRA8888)
4’b0111 = Transparency mode 4 bpp
4’b1000 = Transparency mode 8bpp
4’b1001 = Luminance offset mode 4 bpp
4’b1010 = Luminance offset mode 8 bpp
4’b1011 = 16 bpp (ARGB1555)
4’b1100 = 16 bpp (ARGB4444)
4’b1101 = 16 bpp (APAL8)
4’b1110 = YCbCr422 (the blend engine allows only a single YCbCr layer in any blend operation)
4’b1111 = Reserved
Enable RLE mode for layer.
1’b1:Enabled
1’b0:Disabled
Look Up Table offset. Value gives the offset to the start address of the CLUT or tile (when used
in internal tile mode) in the CLUT/TILE RAM.
Chroma Keying
1’b1: ON
1’b0: OFF
Alpha Blending
2’b00: No alpha Blending
2’b01: Blend only the pixels selected by chroma keying in case BB=1’b1
2’b10: Blend the whole frame
2’b11: Same functionality as 2’b00.
11.3.4.5 Control Descriptor L0_5 Register
Figure 11-8 represents the control Descriptor L0_5 register. This register sets the maximum Chroma
Keying values for RGB.
Refer to Section 11.4.4.5, Alpha and chroma-key blending, for a description of Chroma Keying.
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor