PXD20RM Datasheet, PDF (1025/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 27-49. TCD settings (UART node, TX mode) (continued)
TCD Field
NBYTES[31:0]
SADDR[31:0]
SOFF[15:0]
SSIZE[2:0]
SLAST[31:0]
DADDR[31:0]
DOFF[15:0]
DSIZE[2:0]
DLAST_SGA[31:0]
INT_MAJ
D_REQ
START
Value
8-bit data
16-bit data
1
RAM address
1
0
-M
BDRL address
2
2
1
-M * 2
0
0
1
0
0/1
1
0
Description
Minor loop transfer = 1 or 2 bytes
Byte/Half-word increment
Byte/Half-word transfer
DADDR = BDRL + 0x3 for byte transfer
DADDR = BDRL + 0x2 for half-word
transfer
No increment (FIFO)
Byte/Half-word transfer
No scatter/gather processing
Interrupt disabled/enabled
Only on the last TCD of the chain.
No software request
27.11.6 UART node, RX mode
In UART RX mode, the DMA interface requires a DMA RX channel. A single TCD can control the
reception of an entire Rx buffer. The memory map associated with the TCD chain (RAM area and
LINFlexD registers) is shown in Figure 27-53.
LINFlex2 regs
RAM area
DMA transfer (8/16 bits data format)
Buffer (n)
BDRM
(4 bytes FIFO mode)
BDRM
(2 half-words FIFO mode)
BDRM (M bytes)
BDRM (M half-words)
TCD (n)
Buffer (n+1)
BDRM
(4 bytes FIFO mode)
BDRM
(2 half-words FIFO mode)
BDRM (M bytes)
BDRM (M half-words)
TCD (n+1)
1 DMA RX channel (TCD single and/or linked chain)
Figure 27-53. TCD chain memory map (UART node, RX mode)
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
27-69