PXD20RM Datasheet, PDF (1445/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 42-4. CONTROL Register Field Description (continued)
Field
Description
1 SDCPU - -modulator Power Up. Setting this bit enables the analog block of the SSD and enables the
clocking of the port control logic of the digital part.
1 Analog block of the SSD is enabled.
0 Analog block of the SSD is not enabled.
0 D_RSVD - Reserved bit..
This bit is writable but should be kept as value 0.
1 _{The application must switch off any other blocks possibly interfering with port control of the SSD block.}
42.3.3.2 Interrupt Enable and Flag Register (IRQ)
Figure 42-4 below describes the fields of the interrupt enable and flag (IRQ) register:
Offse 0x02
t
Access: User read/write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R _{BLNIF ITGIF 0}
0
0
0
0
ACOV
IF
BLNI
E
ITGIE
0
0
0
0
0 _ACOV
IE
W w1c w1c
w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 42-4. SSD Interrupt Flag and Enable Register (IRQ)
The function of the IRQ register bits is shown in Table 42-5.
Table 42-5. IRQ Register Field Description
Field
Description
15 BLNIF - Blanking expired Interrupt Flag.
1 This flag is set when the BIS blanking phase has expired.
0 No such event.
14 ITGIF - Integration expired Interrupt Flag.
1 This flag is set when the BIS integration phase has expired.
0 No such event.
8 ACOVIF - Accumulator Overflow Interrupt Flag.
1 This flag is set when during the BIS integration phase the integration logic attempted either to increment
the ITGACC register above 0x7FFF or to decrement it below 0x8000.
0 No such event.
7 BLNIE - Blanking expired Interrupt Enable.
1 A module interrupt will occur if the BLNIF bit is set.
0 The BLNIF flag will not trigger an interrupt on the ips_int output.
PXD20 Microcontroller Reference Manual, Rev. 1
42-7