PXD20RM Datasheet, PDF (756/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Register address: ECSM Base + 0x4a
0
R _RW
W ^BIT
RESET: ₀
1
2
3
4
0 FRC1 FR11 0
BI
BI
0
0
0
0
5
6
7
8
0 FRCN FR1 0
CI NCI
0
0
0
0
9
10 11 12 13 14 15
ERRBIT
0
0
0
0
0
0
0
= Unimplemented
Figure 19-4. ECC Error Generation (EEGR) Register
Table 19-5. EEGR field descriptions
Field
Description
RWBIT
FRC1BI
Redundant writable bit
This bit has no function, but may be read and written.
Force RAM Continuous 1-Bit Data Inversions
0 = No RAM continuous 1-bit data inversions are generated.
1 = 1-bit data inversions in the RAM are continuously generated.
The assertion of this bit forces the RAM controller to create 1-bit data inversions, as defined by the bit
position specified in ERRBIT[0:6], continuously on every write operation.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.
After this bit has been enabled to generate another continuous 1-bit data inversion, it must be cleared
before being set again to properly re-enable the error generation logic.
This bit can only be set if the same SoC configurable input enable signal (as that used to enable single-bit
correction reporting) is asserted.
FR11BI
Note: The only allowable values for the 4 control bit enables {FR11BI, FRC1BI, FRCNCI, FR1NCI} are
{0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. All other values result in undefined behavior.
Force RAM One 1-bit Data Inversion
0 = No RAM single 1-bit data inversion is generated.
1 = One 1-bit data inversion in the RAM is generated.
The assertion of this bit forces the RAM controller to create one 1-bit data inversion, as defined by the
bit position specified in ERRBIT[0:6], on the first write operation after this bit is set.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.
After this bit has been enabled to generate a single 1-bit data inversion, it must be cleared before being
set again to properly re-enable the error generation logic.
This bit can only be set if the same SoC configurable input enable signal (as that used to enable single-bit
correction reporting) is asserted.
Note: The only allowable values for the 4 control bit enables {FR11BI, FRC1BI, FRCNCI, FR1NCI} are
{0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. All other values result in undefined behavior.
19-8
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor