PXD20RM Datasheet, PDF (1363/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

SGM Register Base + 0x00F8
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R _TSFE 0
WN
0
0
0
0
0
FOFE FUFE
0
0
0
0 _CPLE 0
N
0
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 39-34. I2S Interrupt Control Register (I2SINTC)
Field
31
TSFEN
31-26
25
FOFE
24
FUFE
18
CPLEN
15-0
Table 39-38. I2S Enable Register
Description
I2S transfer error interrupt enable.
Reserved.
I2S FIFO Overflow enable.
I2S FIFO Underflow enable.
I2S complete interrupt enable.
Reserved.
39.6.2.34 I2S Status Register (I2SST)
The I2SINTS register shows the status of the I2S interface.
SGM Register Base + 0x00FC
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R TSFE 0
0
0
0
0 FOF FUF 0
0
0
0
0 CPL 0
0
W w1c
w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R0
0
0
0
0
0
0
0
FIFOST
0
0
0 BSY
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 39-35. I2S Status Register (I2SST)
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
39-39