PXD20RM Datasheet, PDF (800/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

• The MB is not locked (see Section 20.5.6.2, Message Buffer lock mechanism)
• The Code field is either EMPTY or else it is FULL or OVERRUN but the CPU has already serviced
the MB (read the C/S word and then unlocked the MB)
If the first MB with a matching ID is not “free to receive” the new frame, then the matching algorithm
keeps looking for another free MB until it finds one. If it can not find one that is free, then it will overwrite
the last matching MB (unless it is locked) and set the Code field to OVERRUN (refer to Table 20-5 and
Table 20-6). If the last matching MB is locked, then the new message remains in the SMB, waiting for the
MB to be unlocked (see Section 20.5.6.2, Message Buffer lock mechanism).
Suppose, for example, that the FIFO is disabled and there are two MBs with the same ID, and FlexCAN
starts receiving messages with that ID. Let us say that these MBs are the second and the fifth in the array.
When the first message arrives, the matching algorithm will find the first match in MB number 2. The code
of this MB is EMPTY, so the message is stored there. When the second message arrives, the matching
algorithm will find MB number 2 again, but it is not “free to receive,” so it will keep looking and find MB
number 5 and store the message there. If yet another message with the same ID arrives, the matching
algorithm finds out that there are no matching MBs that are “free to receive,” so it decides to overwrite the
last matched MB, which is number 5. In doing so, it sets the Code field of the MB to indicate OVERRUN.
The ability to match the same ID in more than one MB can be exploited to implement a reception queue
(in addition to the full featured FIFO) to allow more time for the CPU to service the MBs. By programming
more than one MB with the same ID, received messages will be queued into the MBs. The CPU can
examine the Time Stamp field of the MBs to determine the order in which the messages arrived.
The matching algorithm described above can be changed to be the same one used in previous versions of
the FlexCAN module. When the BCC bit in MCR is negated, the matching algorithm stops at the first MB
with a matching ID that it founds, whether this MB is free or not. As a result, the message queueing feature
does not work if the BCC bit is negated.
Matching to a range of IDs is possible by using ID Acceptance Masks. FlexCAN supports individual
masking per MB. Please refer to Section 20.4.4.13, Rx Individual Mask Registers (RXIMR0–RXIMR63).
During the matching algorithm, if a mask bit is asserted, then the corresponding ID bit is compared. If the
mask bit is negated, the corresponding ID bit is “don’t care.” Please note that the Individual Mask
Registers are implemented in RAM, so they are not initialized out of reset. Also, they can only be
programmed if the BCC bit is asserted and while the module is in Freeze Mode.
FlexCAN also supports an alternate masking scheme with only three mask registers (RGXMASK,
RX14MASK and RX15MASK) for backwards compatibility. This alternate masking scheme is enabled
when the BCC bit in the MCR Register is negated.
20.5.6 Data Coherence
In order to maintain data coherency and FlexCAN proper operation, the CPU must obey the rules described
in Transmit process and Section 20.5.4, Receive process. Any form of CPU accessing an MB structure
within FlexCAN other than those specified may cause FlexCAN to behave in an unpredictable way.
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PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor