PXD20RM Datasheet, PDF (1119/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Reg 127
Index:
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
15
R
MCK
O ^MCK
FPM _{_GT} O
_EN
MCKO_DIV
EVT ⁰
_EN
0
0
0
0
0
0
0
0
W
Reset ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
R _{LP_} 0
W ^DBG
_EN
Reset ₀
0
18
19 20 21 22 23 24 25 26 27 28 29 30
31
0
0
0
0
SLE
EP_
SYN
C
STO
P_S
YNC
0
0
0
0
0
0
0 _PSTA
T
_EN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 30-4. Port Configuration Register (PCR)
Table 30-4. PCR field descriptions
Field
Description
FPM
Full Port Mode.The value of the FPM bit determines if the auxiliary output port uses the full MDO port
or a reduced MDO port to transmit messages.
0 A subset of MDO pins are used to transmit messages.
1 All MDO pins are used to transmit messages.
MCKO_EN
MCKO Enable. This bit enables the MCKO clock to run. When enabled, the frequency of MCKO is
determined by the MCKO_DIV field.
0 MCKO clock is driven to zero.
1 MCKO clock is enabled.
MCKO_DIV MCKO Division Factor. The value of this signal determines the frequency of MCKO relative to the
system clock frequency when MCKO_EN is asserted. In this table, SYS_CLK represents the system
clock frequency.
MCKO_DIV[2:0]
0b000
0b001
0b010
0b011
0b100
0b101
0b110
0b111
MCKO Frequency
SYSCLK1
SYSCLK2
Reserved
SYS_CLK4
Reserved
Reserved
Reserved
SYS_CLK8
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
30-7