PXD20RM Datasheet, PDF (1359/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Field
31-5
4
SRST
3-1
0
IEN
Table 39-33. I2S Enable Register
Description
Reserved.
I2S module Soft Reset.
Writing 1 to this bit soft resets the module logic. Memory mapped registers are not be affected.
0: Normal function
1: Soft Reset asserted
Reserved.
I2S enable.
0: I2S interface disabled
1: 2S interface enabled
39.6.2.30 I2S Control Register (I2SCTL)
The I2SCTL register controls I2S operations
SGM Register Base + 0x00EC
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
FIFOTH
W
0
0
0
0 _{ACE ACSE CHS} 0
N
L EL
PM
0
0
PSYN
C
POL
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 39-31. I2S control register (I2SCTL)
Field
31-15
15-14
FIFOTH
13-10
9
ACEN
8
ACSEL
Table 39-34. I2S Control Register
Description
Reserved.
I2S FIFO threshold level.
After accumulating the number of data specified by this number, the I2S starts sending data out ofthe interface.
00: Threshold is 1, start as soon as data is received from SGM
01: Threshold is 2, start after 2 data units are received from SGM
10: Threshold is 3, start after 3 data units are received from SGM
11: Threshold is 4, start after 4 data units are received from SGM
Reserved.
Auxiliary Clock (MCLK).
0 Auxiliary clock disabled.
1 Auxiliary clock enabled.
Auxiliary Clock (MCLK) Selection.
0: Auxiliary clock is 256 times the sampling clock
1: Auxiliary clock is 512 times the sampling clock
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
39-35