PXD20RM Datasheet, PDF (1247/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 35-34. Interrupt and DMA Request Conditions
Condition
TX Buffer Fill
TX Buffer Underrun
RX Buffer Drain
RX Buffer Overflow
AHB Buffer Overflow
AHB Command Error
AHB Command Mode Error
IP Command Usage Error
IP Command Error
IP Command Mode Error
IP Command Trigger during AHB Access Error
IP Command Trigger could not be executed Error
IP Access during AHB Grant Error
IP Command related Transaction Finished
Flag
(QSPI_SPISR)
TBFF
TBUF
RBDF
RBOF
ABOF
ABCEF
ABMEF
IUEF
ICEF
IMEF
IPAEF
IPIEF
IPGEF
TFF
DMA
X
Each condition has a flag bit in the QSPI_SFMFR and a Request Enable bit in the QSPI_SFMRSER. The
RX Buffer Drain Flag (RBDF) has separate enable bits for generating IRQ and DMA requests. Note that
not each single flag is represented by an individual IRQ line.
35.5.3.5.1 Transmit Buffer Fill Interrupt Request
The Transmit Buffer Fill IRQ indicates that the TX Buffer can accept new data. It is asserted if the
QSPI_SFMFR[TBFF] flag is asserted and if the corresponding enable bit (QSPI_SFMRSER[TBFIE]) is
set. Refer to Section 35.5.3.6, TX Buffer Operation, for details about the assertion of the
QSPI_SFMFR[TBFF] flag.
35.5.3.5.2 Receive Buffer Drain Interrupt or DMA Request
The Receive Buffer Drain IRQ derived from the QSPI_SFMFR[RBDF] flag indicates that the RX Buffer
of the QuadSPI module has data available from the serial flash device to be read by the host. It remains set
as long as the QSPI_RBSR[RXWE] bit is set. The QSPI_SFMRSER[RBDIE] bit enables the related IRQ.
Aside from the IRQ it is possible to handle RX Buffer drain by DMA. If the QSPI_SFMRSER[RBDDE]
bit is set each write of the module into the RX Buffer triggers a DMA request. The application must set
the environment appropriately (e.g. the DMA controller) for the DMA transfers.
35.5.3.5.3 Buffer Overflow/Underrun Interrupt Request
The Buffer Overflow/Underrun IRQ is a combination of the following flags (all located in the
QSPI_SPIFR register with the related enable bits in the QSPI_SPIRSER register):
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
35-37