PXD20RM Datasheet, PDF (787/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

20.4.4.5 Rx 14 Mask (RX14MASK)
This register is provided for legacy support and for low cost MCUs that do not have the individual masking
per Message Buffer feature. For MCUs supporting individual masks per MB, setting the BCC bit in MCR
causes the RX14MASK Register to have no effect on the module operation.
RX14MASK is used as acceptance mask for the Identifier in Message Buffer 14. When the FEN bit in
MCR is set (FIFO enabled), the RXG14MASK also applies to element 6 of the ID filter table. This register
has the same structure as the Rx Global Mask Register. It must be programmed while the module is in
Freeze Mode, and must not be modified when the module is transmitting or receiving frames.
• Address Offset: 0x14
• Reset Value: 0xFFFF_FFFF
20.4.4.6 Rx 15 Mask (RX15MASK)
This register is provided for legacy support and for low cost MCUs that do not have the individual masking
per Message Buffer feature. For MCUs supporting individual masks per MB, setting the BCC bit in MCR
causes the RX15MASK Register to have no effect on the module operation.
When the BCC bit is negated, RX15MASK is used as acceptance mask for the Identifier in Message Buffer
15. When the FEN bit in MCR is set (FIFO enabled), the RXG14MASK also applies to element 7 of the
ID filter table. This register has the same structure as the Rx Global Mask Register. It must be programmed
while the module is in Freeze Mode, and must not be modified when the module is transmitting or
receiving frames.
• Address Offset: 0x18
• Reset Value: 0xFFFF_FFFF
20.4.4.7 Error Counter Register (ECR)
This register has 2 8-bit fields reflecting the value of two FlexCAN error counters: Transmit Error Counter
(Tx_Err_Counter field) and Receive Error Counter (Rx_Err_Counter field). The rules for increasing and
decreasing these counters are described in the CAN protocol and are completely implemented in the
FlexCAN module. Both counters are read only except in Freeze Mode, where they can be written by the
CPU.
Writing to the Error Counter Register while in Freeze Mode is an indirect operation. The data is first
written to an auxiliary register and then an internal request/acknowledge procedure across clock domains
is executed. All this is transparent to the user, except for the fact that the data will take some time to be
actually written to the register. If desired, software can poll the register to discover when the data was
actually written.
FlexCAN responds to any bus state as described in the protocol, e.g. transmit ‘Error Active’ or ‘Error
Passive’ flag, delay its transmission start time (‘Error Passive’) and avoid any influence on the bus when
in ‘Bus Off’ state. The following are the basic rules for FlexCAN bus state transitions.
• If the value of Tx_Err_Counter or Rx_Err_Counter increases to be greater than or equal to 128, the
FLT_CONF field in the Error and Status Register is updated to reflect ‘Error Passive’ state.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
20-21