PXD20RM Datasheet, PDF (849/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

21.4.1.2.1 Program software locking
A software mechanism is provided to independently lock/unlock each High, Mid and Low Address Space
block against program and erase.
Software Locking is done through the LML (Low/Mid Address Space Block Lock) or HBL (High Address
Space Block Lock) registers. These may be written through register writes, and may be read through
register reads.
21.4.1.2.2 Program suspend/resume
The program sequence may be suspended to allow read access to the FC. It is not possible to erase during
a program suspend, or program during a program suspend. Read While Write may also be used to read
the array during a program sequence providing the read is to a different partition.
A program suspend can be initiated by changing the value of the MCR[PSUS] bit from a 0 to a 1.
MCR[PSUS] can be set high at any time when MCR[PGM] and MCR[EHV] are high. A 0 to 1 transition
of MCR[PSUS] causes the flash module to start the sequence to enter program suspend, which is a read
state. The user must wait until MCR[DONE] = 1 before the module is suspended. At this time FC reads
may be attempted. MCR[DONE] goes high no more than Tpsus (Appendix A) after MCR[PSUS] is set to
a 1. Once suspended, the FC may only be read. Reads to the block(s) being programmed/erased return
indeterminate data.
The program sequence is resumed by writing a logic 0 to MCR[PSUS]. MCR[EHV] must be set to a 1
before clearing MCR[PSUS] to resume operation. When the operation resumes, the flash module
continues the program sequence from one of a set of predefined points. This may extend the time required
for the program operation.
WARNING
Repeated suspends at a high frequency may result in the operation timing
out, and the flash module will respond by completing the operation with a
fail code (MCR[PEG] = 0). The minimum time between suspends to ensure
this does not occur is 100uS.
21.4.1.3 Flash Erase
Erase changes the value stored in all bits of the selected block(s) to logic 1. An erase sequence operates on
any combination of blocks in the Low, Mid or High Address Space, or the shadow block. The erase
sequence is fully automated within the flash. The user only needs to select the blocks to be erased and
initiate the erase sequence. Locked/disabled blocks cannot be erased. If multiple blocks are selected for
erase during an erase sequence, the blocks are erased sequentially starting with the lowest numbered block
and terminating with the highest. The erase sequence consists of the following sequence of events:
1. Change the value in the MCR[ERS] bit from 0 to a 1.
2. Select the block, or blocks to be erased by writing ones to the appropriate registers in LMS or HBS
registers. If the shadow block is to be erased, this step may be skipped, and LMS and HBS are
ignored.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
21-37