PXD20RM Datasheet, PDF (829/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 21-10. ADR Field Descriptions
Field
Description
SAD
Shadow Address. The SAD bit qualifies the address captured during an ECC Event Error, Single Bit Correction,
or State Machine operation.
The SAD register is not writable.
0 Address Captured is from Main Array Space.
1 Address Captured is from Shadow Array Space.
ADDR[20:3]
Address. The ADR register provides the first failing address in the event of ECC event error (MCR[EER] set),
single bit correction (MCR[SBC] set), as well as providing the address of a failure that may have occurred in a
state machine operation (MCR[PEG] cleared). ECC event errors take priority over single bit corrections, which
take priority over state machine errors. This is especially valuable in the event of a RWW operation, where the
read senses an ECC error or single bit correction, and the state machine fails simultaneously. This address is
always a Double Word address that selects 64 bits.
The ADR register is writable, and can be used in the UTest ECC Logic Check. If the ECC logic check is enabled
(UT0[EIE] = 1) then the ADR register will not update for ECC event error, single bit correction, or state machine
errors.
If MCR[EER] or MCR[SBC] are set, the ADR register is locked from writing. MCR[PEG] does not affect the
writability of the ADR register.
21.3.2.8 Platform Flash Configuration Registers (PFCRP0 and PFCRP1)
The PFLASH configuration register for port 0 (PFCRP0) is used to specify operation of port p0 of the flash
memory module. This register also has two bits (ARB and PRI) to control arbitration between the p0/p1
ports.
The PFLASH configuration register for port 1 (PFCRP1) is used to specify operation of port p1 of the flash
memory module.
The PFCRPn registers are shown in Figure 21-10, Figure 21-11, and Table 21-11.
Master ID mapping can be found in Table 9-1.
Offset: FLASH_REGS_BASE + 0x001C
Access: User read/write
0123
4
5
6
7
8
9
10
11
12
13
14
15
R
W
LBCFG
0
0
ARB PRI
Reset 0 0 0 0 0
0
0
0
1
1
1
1
1
1
1
1
16 17 18 19 20
21
22
23
24
25
26
27
28
29
30
R
0
0
0
W
APC
WWSC
RWSC
IPFEN
PFLIM
Reset 0 1 1 1 1
0
1
1
0
1
0
1
0
1
1
Figure 21-10. Platform Flash Configuration Register for Port 0 (PFCRP0)
31
BFEN
1
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
21-17