PXD20RM Datasheet, PDF (753/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 19-3. ECC Configuration (ECR) field descriptions (continued)
Field
EF1BR
Description
Enable Flash 1-bit Reporting
0 = Reporting of single-bit flash corrections is disabled.
1 = Reporting of single-bit flash corrections is enabled.
ERNCR
This bit can only be set if the SoC-configurable input enable signal is asserted. The occurrence of a
single-bit flash correction generates a ECSM ECC interrupt request as signalled by the assertion of
ESR[F1BC]. The address, attributes and data are also captured in the FEAR, FEMR, FEAT and FEDR
registers.
Enable RAM Non-Correctable Reporting
0 = Reporting of non-correctable RAM errors is disabled.
1 = Reporting of non-correctable RAM errors is enabled.
EFNCR
The occurrence of a non-correctable multi-bit RAM error generates a ECSM ECC interrupt request as
signalled by the assertion of ESR[RNCE]. The faulting address, attributes and data are also captured
in the REAR, RESR, REMR, REAT and REDR registers.
Enable Flash Non-Correctable Reporting
0 = Reporting of non-correctable flash errors is disabled.
1 = Reporting of non-correctable flash errors is enabled.
The occurrence of a non-correctable multi-bit flash error generates a ECSM ECC interrupt request as
signalled by the assertion of ESR[FNCE]. The faulting address, attributes and data are also captured in
the FEAR, FEMR, FEAT and FEDR registers.
19.4.2.4 ECC Status Register (ESR)
The ECC Status Register is an 8-bit control register for signaling which types of properly-enabled ECC
events have been detected. The ESR signals the last, properly-enabled memory event to be detected. ECC
interrupt generation is separated into single-bit error detection/correction, uncorrectable error detection
and the combination of the two as defined by the following boolean equations. In these equations, “&”
refers to a bitwise AND operator and “|” refers to a bitwise OR operator; bitwise AND has precedence of
bitwise OR.
Bitwise AND has precedence of bitwise OR.
ECSM_ECC1BIT_IRQ
= ECR[ER1BR] & ESR[R1BC]// ram, 1-bit correction
| ECR[EF1BR] & ESR[F1BC]// flash, 1-bit correction
ECSM_ECCRNCR_IRQ
= ECR[ERNCR] & ESR[RNCE]// ram, noncorrectable error
ECSM_ECCFNCR_IRQ
= ECR[EFNCR] & ESR[FNCE]// flash, noncorrectable error
ECSM_ECC2BIT_IRQ
= ECSM_ECCRNCR_IRQ// ram, noncorrectable error
| ECSM_ECCFNCR_IRQ// flash, noncorrectable error
ECSM_ECC_IRQ
= ECSM_ECC1BIT_IRQ // 1-bit correction
| ECSM_ECC2BIT_IRQ// noncorrectable error
where the combination of a properly-enabled category in the ECR and the detection of the corresponding
condition in the ESR produces the interrupt request.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
19-5