PXD20RM Datasheet, PDF (1358/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Field
Description
11
Flag of reaching the end of at Attack Phase in DDS mode for channel 3.
EOAFCH3
10
Flag of reaching the end of at Attack Phase in DDS mode for channel 2.
EOAFCH2
9
Flag of reaching the end of at Attack Phase in DDS mode for channel 1.
EOAFCH1
8
Flag of reaching the end of at Attack Phase in DDS mode for channel 0.
EOAFCH0
7
Flag of reaching the end of the inter-note no-output phase for Channel 3 in DDS mode.
EONFCH3
6
Flag of reaching the end of the inter-note no-output phase for Channel 2 in DDS mode.
EONFCH2
5
Flag of reaching the end of the inter-note no-output phase for Channel 1 in DDS mode.
EONFCH1
4
Flag of reaching the end of the inter-note no-output phase for Channel 0 in DDS mode.
EONFCH0
3
Flag of reaching the Target number of note Pulses Count for Channel 3 in DDS mode.
PCFCH3
2
Flag of reaching the Target number of note Pulses Count for Channel 2 in DDS mode.
PCFCH2
1
Flag of reaching the Target number of note Pulses Count for Channel 1 in DDS mode.
PCFCH1
0
Flag of reaching the Target number of note Pulses Count for Channel 0 in DDS mode.
PCFCH0
39.6.2.29 I2S Enable Register (I2SEN)
The I2SEN register enables the I2S operations
SGM Register Base + 0x00E8
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
SRST
IEN
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 39-30. I2S Enable Register (I2SEN)
39-34
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor