PXD20RM Datasheet, PDF (1011/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 27-42. Register settings (master node, TX mode)
LIN frame
Master to Slave
Slave to Master
Slave to Slave
LINCR2
DDRQ=1
DTRQ=0
HTRQ=0
DDRQ=0
DTRQ=0
HTRQ=0
DDRQ=1
DTRQ=0
HTRQ=0
BIDR
DFL = payload size
ID = address
CCS = checksum
DIR = 1 (TX)
DFL = payload size
ID = address
CCS = checksum
DIR = 0 (RX)
DFL = payload size
ID = address
CCS = checksum
DIR = 0 (RX)
The concept FSM to control the DMA TX interface is shown in Figure 27-44. The DMA TX FSM will
move to IDLE state immediately at next clock edge if DMATXE[0] = 0.
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
27-55