PXD20RM Datasheet, PDF (588/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Table 13-7. Mapping of Address to DRAM Chip Select
CS_SELECT¹
DRAM Chip Select
0
dram_cs_select² = 0
1
dram_cs_select = address[12]
2
dram_cs_select = address[13]
3
dram_cs_select = address[14]
4
dram_cs_select = address[15]
5
dram_cs_select = address[16]
6
dram_cs_select = address[27]
7
dram_cs_select = address[28]
8
dram_cs_select = address[29]
9
dram_cs_select = address[30]
1 _{For the field of register 0x60, see Table 13-16.}
2 _{if DRAM_CS_SELECT = 0  use CS0.}
if DRAM_CS_SELECT = 1  use CS1.
13.3.2.2 Timing Configuration
13.3.2.2.1 DRAMC Time Configuration Register 0 (DRAMC_TC0)
Address: Base + 0x0004
0
1
2
3
4
5
6
7
8
9
10
11
R0
0
W
REFRESH
Reset 0
0
0
0
0
0
0
0
0
0
0
0
Access: User read/write
12
13
14
15
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
CMD
W
PRE
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-4. DRAMC Time Configuration Register 0 (DRAMC_TC0)
Table 13-8. DRAMC_TC0 field descriptions
Field
REFRESH
CMD
Description
Refresh interval of the DRAM. Program in this register the number of system bus clocks between
any two refresh requests.
Time-out after sending a command to the DRAM in bypass mode. For command sent to the DRAM
using the DDR_COMMAND and DDR_COMPACT_COMMAND register, the normal checking of the
timing parameters is not done. Instead, any new command to the DRAM is disabled for
DRAM_COMMAND_TIME[7:0] dram clock periods. This parameter needs to be programmed for
the worst-case time-out.
13-8
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor