PXD20RM Datasheet, PDF (293/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

Address
Base + 0x0080
Base + 0x0084
Base + 0x0088
Base + 0x008C
Base + 0x0090–
Base + 0x00CC
Table 10-2. DSPI detailed memory map (continued)
Register description
DSPI receive FIFO register 1 (DSPIx_RXFR1)
DSPI receive FIFO register 2 (DSPIx_RXFR2)
DSPI receive FIFO register 3 (DSPIx_RXFR3)
DSPI receive FIFO register 4 (DSPIx_RXFR4)
Reserved
Location
on page
10-23
on page
10-23
on page
10-23
on page
10-23
—
10.8.2 Register description
10.8.2.1 DSPI Module Configuration Register (DSPIx_MCR)
The DSPIx_MCR contains bits which configure attributes of the DSPI operation. The values of the HALT
and MDIS bits can be changed at any time, but their effect begins on the next frame boundary. The HALT
and MDIS bits in the DSPIx_MCR are the only bit values software can change while the DSPI is running.
Address: Base + 0x0000
0
1
2
3
4
5
6
7
8
R _{MST CONT_}
W ^{R SCKE}
DCONF
FRZ
MTF
E
0
RO
OE
0
Reset 0
0
0000000
Access: R/W
9
10 11 12 13 14 15
0
PCSI PCSI PCSI PCSI PCSI PCSI
S5 S4 S3 S2 S1 S0
0000000
16
R0
W
Reset 0
17
18
19
20
21
22
23
24
25
26
27
28
29
CLR_ CLR_
MDIS
DIS_ DIS_
TXF RXF
TXF
RXF
SMPL_PT
0
0
0
0
0
0
w1c w1c
1
000000000000
Figure 10-3. DSPI Module Configuration Register (DSPIx_MCR)
Table 10-3 describes the fields in the DSPI module configuration register.
30 31
0
HALT
01
Freescale Semiconductor
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
10-7