PXD20RM Datasheet, PDF (312/1628 Pages) Freescale Semiconductor, Inc – PXD20 Microcontroller

10.9.1.2 Slave Mode
In slave mode the DSPI responds to transfers initiated by an SPI master. The DSPI operates as bus slave
when the MSTR bit in the DSPIx_MCR is negated. The DSPI slave is selected by a bus master by having
the slave’s CS0_x asserted. In slave mode the SCK is provided by the bus master. All transfer attributes
are controlled by the bus master, except the clock polarity, clock phase and the number of bits to transfer
which must be configured in the DSPI slave to communicate correctly.
10.9.1.3 Module Disable Mode
The module disable mode is used for MCU power management. The clock to the non-memory mapped
logic in the DSPI is stopped while in module disable mode. The DSPI enters the module disable mode
when the MDIS bit in DSPIx_MCR is set.
Refer to Section 10.9.8, Power Saving Features, for more details on the module disable mode.
10.9.1.4 External Stop Mode
For devices with low-power modes, the DSPI supports the Global Signal Stop Mode mechanism. The
DSPI will not acknowledge the request to enter External Stop Mode until it has reached a frame boundary.
When the DSPI has reached a frame boundary it will halt all operations and indicate that it is ready to have
its clocks shut off. The DSPI exits External Stop Mode and resumes normal operation once the clocks are
turned on. Serial communications or register accesses made while in External Stop Mode are ignored even
if the clocks have not been shut off yet. See Section 10.9.8, Power Saving Features, for more details on the
External Stop Mode.
10.9.1.5 Debug Mode
The debug mode is used for system development and debugging. If the MCU enters debug mode while the
FRZ bit in the DSPIx_MCR is set, the DSPI stops all serial transfers and enters a stopped state. If the MCU
enters debug mode while the FRZ bit is cleared, the DSPI behavior is unaffected and remains dictated by
the module-specific mode and configuration of the DSPI. The DSPI enters debug mode when a debug
request is asserted by an external controller.
Refer to Figure 10-12 for a state diagram.
10.9.2 Start and Stop of DSPI Transfers
The DSPI has two operating states: STOPPED and RUNNING. The states are independent of DSPI
configuration. The default state of the DSPI is STOPPED. In the STOPPED state no serial transfers are
initiated in master mode and no transfers are responded to in slave mode. The STOPPED state is also a
safe state for writing the various configuration registers of the DSPI without causing undetermined results.
The TXRXS bit in the DSPIx_SR is cleared in this state. In the RUNNING state, serial transfers take place.
The TXRXS bit in the DSPIx_SR is set in the RUNNING state.
Figure 10-12 shows a state diagram of the start and stop mechanism.
10-26
PXD20 Microcontroller Reference Manual, Rev. 1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor